Semiconductor element memory device

ABSTRACT

A memory device according to the present invention includes memory cells, each of the memory cells includes a semiconductor base material that is formed on a substrate and that stands on the substrate in a vertical direction, voltages applied to a first gate conductor layer, a second gate conductor layer, a first impurity layer, and a second impurity layer in each of the memory cells are controlled to perform a write operation of retaining, inside a channel semiconductor layer, a group of positive holes generated by an impact ionization phenomenon or by a gate-induced drain leakage current, and the voltages applied to the first gate conductor layer, the second gate conductor layer, the first impurity layer, and the second impurity layer are controlled to perform an erase operation of discharging the group of positive holes from inside the channel semiconductor layer. The first gate conductor layer partially surrounds a side surface of the semiconductor base material, and the second gate conductor layer entirely surrounds the side surface of the semiconductor base material.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application claims priority to PCT/JP2021/015529 filed Apr. 15, 2021, the enter content of which is incorporated herein by reference.

TECHNICAL FIELD

The present invention relates to a semiconductor memory device including a semiconductor element.

BACKGROUND ART

Recently, there has been a demand for highly integrated and high-performance memory elements in the development of LSI (Large Scale Integration) technology.

Typical planar MOS transistors include a channel that extends in a horizontal direction along the upper surface of the semiconductor substrate. In contrast, SGTs include a channel that extends in a direction perpendicular to the upper surface of the semiconductor substrate (see, for example, PTL 1 and NPL 1). Accordingly, the density of semiconductor devices can be made higher with SGTs than with planar MOS transistors. Such SGTs can be used as selection transistors to implement highly integrated memories, such as a DRAM (Dynamic Random Access Memory, see, for example, NPL 2) to which a capacitor is connected, a PCM (Phase Change Memory, see, for example, NPL 3) to which a resistance change element is connected, an RRAM (Resistive Random Access Memory, see, for example, NPL 4), and an MRAM (Magneto-resistive Random Access Memory, see, for example, NPL 5) that changes the resistance by changing the orientation of a magnetic spin with a current. Further, there exists, for example, a DRAM memory cell (see, for example, NPL 6) constituted by a single MOS transistor and including no capacitor. The present application relates to a dynamic flash memory that can be constituted only by a MOS transistor and that includes no resistance change element or capacitor.

FIGS. 7A to 7D illustrate a write operation of a DRAM memory cell constituted by a single MOS transistor and including no capacitor described above, FIGS. 8A and 8B illustrate a problem in the operation, and FIGS. 9A to 9C illustrate a read operation (see NPL 7 to NPL 10). FIG. 7A illustrates a “1” write state. Here, the memory cell is formed on an SOI substrate 100, is constituted by a source N⁺ layer 103 (hereinafter, a semiconductor region that contains a donor impurity in high concentrations is referred to as “N⁺ layer”) to which a source line SL is connected, a drain N⁺ layer 104 to which a bit line BL is connected, a gate conductor layer 105 to which a word line WL is connected, and a floating body 102 of a MOS transistor 110, and includes no capacitor. The single MOS transistor 110 constitutes the DRAM memory cell. Directly under the floating body 102, a SiO₂ layer 101 of the SOI substrate is in contact with the floating body 102. To write “1” to the memory cell constituted by the single MOS transistor 110, the MOS transistor 110 is operated in the saturation region. That is, a channel 107, for electrons, extending from the source N⁺ layer 103 has a pinch-off point 108 and does not reach the drain N⁺ layer 104 to which the bit line is connected. When a high voltage is applied to both the bit line BL connected to the drain N⁺ layer and the word line WL connected to the gate conductor layer 105, and the MOS transistor 110 is operated at the gate voltage that is about one-half of the drain voltage, the electric field intensity becomes maximum at the pinch-off point 108 that is in the vicinity of the drain N⁺ layer 104. As a result, accelerated electrons that flow from the source N⁺ layer 103 toward the drain N⁺ layer 104 collide with the Si lattice, and with kinetic energy lost at the time of collision, electron-positive hole pairs are generated (impact ionization phenomenon). Most of the generated electrons (not illustrated) reach the drain N⁺ layer 104. Further, a very small proportion of the electrons that are very hot jump over a gate oxide film 109 and reach the gate conductor layer 105. Simultaneously, positive holes 106 are generated with which the floating body 102 is charged. In this case, the generated positive holes contribute to an increase in the majority carriers because the floating body 102 is P-type Si. When the floating body 102 is filled with the generated positive holes 106 and the voltage of the floating body 102 becomes higher than that of the source N⁺ layer 103 by Vb or more, further generated positive holes are discharged to the source N⁺ layer 103. Here, Vb is the built-in voltage of the PN junction between the source N⁺ layer 103 and the P layer, namely, the floating body 102, and is equal to about 0.7 V. FIG. 7B illustrates a state in which the floating body 102 is charged to saturation with the generated positive holes 106.

Now, a “0” write operation of the memory cell 110 will be described with reference to FIG. 7C. For the common selection word line WL, the memory cell 110 to which “1” is written and the memory cell 110 to which “0” is written are present at random. FIG. 7C illustrates a state of rewriting from the “1” write state to a “0” write state. To write “0”, the voltage of the bit line BL is set to a negative bias, and the PN junction between the drain N⁺ layer 104 and the P layer, namely, the floating body 102, is forward biased. As a result, the positive holes 106 in the floating body 102 generated in advance in the previous cycle flow into the drain N⁺ layer 104 that is connected to the bit line BL. When the write operation ends, the two memory cells are in a state in which the memory cell 110 (FIG. 7B) is filled with the generated positive holes 106, and from the memory cell 110 (FIG. 7C), the generated positive holes are discharged. The potential of the floating body 102 of the memory cell 110 filled with the positive holes 106 becomes higher than that of the floating body 102 in which generated positive holes are not present. Therefore, the threshold voltage for the memory cell 110 to which “1” is written becomes lower than the threshold voltage for the memory cell 110 to which “0” is written. This is illustrated in FIG. 7D.

Now, a problem in the operation of the memory cell constituted by the single MOS transistor 110 will be described with reference to FIGS. 8A and 8B. As illustrated in FIG. 8A, the capacitance C_(FB) of the floating body is equal to the sum of the capacitance C_(WL) between the gate to which the word line is connected and the floating body, the junction capacitance C_(SL) of the PN junction between the source N⁺ layer 103 to which the source line is connected and the floating body 102, and the junction capacitance C_(BL) of the PN junction between the drain N⁺ layer 104 to which the bit line is connected and the floating body 102 and is expressed as follows.

C _(FB) =C _(WL) +C _(BL) +C _(SL)  (10)

The capacitive coupling ratio β_(WL) between the gate to which the word line is connected and the floating body is expressed as follows.

β_(WL) =C _(WL)/(C _(WL) +C _(BL) +C _(SL))  (11)

Therefore, a change in the word line voltage V_(WL) at the time of reading or writing affects the voltage of the floating body 102 that functions as a storage node (contact point) of the memory cell. This is illustrated in FIG. 8B. When the word line voltage V_(WL) rises from 0 V to V_(WL)H at the time of reading or writing, the voltage V_(FB) of the floating body 102 rises from V_(FB1), which is the voltage in the initial state before the word line voltage changes, to V_(FB2) due to capacitive coupling with the word line. The voltage change amount ΔV_(FB) is expressed as follows.

$\begin{matrix} {{\Delta V_{FB}} = {{V_{{FB}2} - V_{{FB}1}} = {\beta_{WL} \times V_{WLH}}}} & (12) \end{matrix}$

Here, for β_(WL) in expression (11), contribution of C_(WL) is large and, for example, C_(WL):C_(BL):C_(SL)=8:1:1 holds. This results in βW_(L)=0.8. When the word line changes, for example, from 5 V at the time of writing to 0 V after the end of writing, the floating body 102 receives an amplitude noise of 5 V×β_(WL)=4 V due to capacitive coupling between the word line WL and the floating body 102. Accordingly, a sufficient margin is not provided to the potential difference between the “1” potential and the “0” potential of the floating body 102 at the time of writing, which is a problem.

FIGS. 9A to 9C illustrate a read operation where FIG. 9A illustrates a “1” write state and FIG. 9B illustrates a “0” write state. In actuality, however, even when Vb is set for the floating body 102 to write “1”, once the word line returns to 0 V at the end of writing, the floating body 102 is lowered to a negative bias. When “0” is written, the floating body 102 is lowered to a further negative bias, and it is difficult to provide a sufficiently large margin to the potential difference between “1” and “0” at the time of writing as illustrated in FIG. 9C. Therefore, there has been difficulty in commercially introducing DRAM memory cells actually including no capacitor.

CITATION LIST Patent Literature

-   [PTL 1] Japanese Unexamined Patent Application Publication No.     2-188966 -   [PTL 2] Japanese Unexamined Patent Application Publication No.     3-171768 -   [PTL 3] Japanese Patent No. 3957774

Non Patent Literature

-   [NPL 1] Hiroshi Takato, Kazumasa Sunouchi, Naoko Okabe, Akihiro     Nitayama, Katsuhiko Hieda, Fumio Horiguchi, and Fujio Masuoka: IEEE     Transaction on Electron Devices, Vol. 38, No. 3, pp. 573-578 (1991) -   [NPL 2] H. Chung, H. Kim, H. Kim, K. Kim, S. Kim, K. Dong, J.     Kim, Y. C. Oh, Y. Hwang, H. Hong, G. Jin, and C. Chung: “4F2 DRAM     Cell with Vertical Pillar Transistor (VPT)”, 2011 Proceeding of the     European Solid-State Device Research Conference, (2011) -   [NPL 3] H. S. Philip Wong, S. Raoux, S. Kim, Jiale Liang, J. R.     Reifenberg, B. Rajendran, M. Asheghi and K. E. Goodson: “Phase     Change Memory”, Proceeding of IEEE, Vol. 98, No. 12, December, pp.     2201-2227 (2010) -   [NPL 4] T. Tsunoda, K. Kinoshita, H. Noshiro, Y. Yamazaki, T.     Iizuka, Y. Ito, A. Takahashi, A. Okano, Y. Sato, T. Fukano, M. Aoki,     and Y. Sugiyama: “Low Power and High Speed Switching of Ti-doped NiO     ReRAM under the Unipolar Voltage Source of less than 3V”, IEDM     (2007) -   [NPL 5] W. Kang, L. Zhang, J. Klein, Y. Zhang, D. Ravelosona, and W.     Zhao: “Reconfigurable Codesign of STT-MRAM Under Process Variations     in Deeply Scaled Technology”, IEEE Transaction on Electron Devices,     pp. 1-9 (2015) -   [NPL 6] M. G. Ertosum, K. Lim, C. Park, J. Oh, P. Kirsch, and K. C.     Saraswat: “Novel Capacitorless Single-Transistor Charge-Trap DRAM     (1T CT DRAM) Utilizing Electron”, IEEE Electron Device Letter, Vol.     31, No. 5, pp. 405-407 (2010) -   [NPL 7] J. Wan, L. Rojer, A. Zaslavsky, and S. Critoloveanu: “A     Compact Capacitor-Less High-Speed DRAM Using Field Effect-Controlled     Charge Regeneration”, Electron Device Letters, Vol. 35, No. 2, pp.     179-181 (2012) -   [NPL 8] T. Ohsawa, K. Fujita, T. Higashi, Y. Iwata, T. Kajiyama, Y.     Asao, and K. Sunouchi: “Memory design using a one-transistor gain     cell on SOI”, IEEE JSSC, vol. 37, No. 11, pp. 1510-1522 (2002). -   [NPL 9] T. Shino, N. Kusunoki, T. Higashi, T. Ohsawa, K. Fujita, K.     Hatsuda, N. Ikumi, F. Matsuoka, Y. Kajitani, R. Fukuda, Y.     Watanabe, Y. Minami, A. Sakamoto, J. Nishimura, H. Nakajima, M.     Morikado, K. Inoh, T. Hamamoto, A. Nitayama: “Floating Body RAM     Technology and its Scalability to 32 nm Node and Beyond”, IEEE IEDM     (2006). -   [NPL 10] E. Yoshida and T. Tanaka: “A design of a capacitorless     1T-DRAM cell using gate-induced drain leakage (GIDL) current for     low-power and highspeed embedded memory,” IEEE IEDM, pp. 913-916,     December 2003. -   [NPL 11] E. Yoshida and T. Tanaka: “A Capacitorless 1T-DRAM     Technology Using Gate-Induced Drain-Leakage (GIDL) Current for     Low-Power and High-Speed Embedded Memory”, IEEE Transactions on     Electron Devices, Vol. 53, No. 4, pp. 692-697, April 2006.

SUMMARY OF INVENTION Technical Problem

In capacitor-less single-transistor DRAMs (gain cells), capacitive coupling between the word line and the floating body is strong. When the potential of the word line is changed at the time of data reading or at the time of data writing, the change is transmitted as direct noise to the floating body, which is a problem. This causes a problem of erroneous reading or erroneous rewriting of storage data and makes it difficult to commercially introduce capacitor-less single-transistor DRAMs (gain cells).

Solution to Problem

To solve the above-described problem, a semiconductor element memory device according to the present invention is

a memory device including a plurality of memory cells arranged in a matrix, each of the memory cells including:

a semiconductor base material that stands on a substrate in a vertical direction or that extends in a horizontal direction along the substrate;

a first impurity layer and a second impurity layer that are disposed at respective ends of the semiconductor base material;

a first gate insulating layer that is in contact with or in close vicinity to the first impurity layer and that partially or entirely surrounds an entire periphery of a side surface of the semiconductor base material between the first impurity layer and the second impurity layer;

a second gate insulating layer that surrounds the entire periphery of the side surface of the semiconductor base material and that is in contact with or in close vicinity to the second impurity layer;

a first gate conductor layer that partially covers the side surface of the semiconductor base material with the first gate insulating layer therebetween;

a second gate conductor layer that covers the entire periphery of the side surface of the semiconductor base material with the second gate insulating layer therebetween; and

a channel semiconductor layer that is the semiconductor base material and that is covered by the first gate insulating layer and the second gate insulating layer, in which

in each memory cell,

voltages applied to the first gate conductor layer, the second gate conductor layer, the first impurity layer, and the second impurity layer are controlled to retain, inside the channel semiconductor layer, a group of positive holes generated by an impact ionization phenomenon or by a gate-induced drain leakage current,

in a write operation, a voltage of the channel semiconductor layer is made equal to a first data retention voltage that is higher than the voltage of either the first impurity layer or the second impurity layer or that is higher than the voltages of both the first impurity layer and the second impurity layer,

in an erase operation, the voltages applied to the first impurity layer, the second impurity layer, the first gate conductor layer, and the second gate conductor layer are controlled to discharge the group of positive holes through either the first impurity layer or the second impurity layer or both the first impurity layer and the second impurity layer, and the voltage of the channel semiconductor layer is made equal to a second data retention voltage that is lower than the first data retention voltage,

the first impurity layer of the memory cell is connected to a source line wiring layer, the second impurity layer thereof is connected to a bit line wiring layer, the first gate conductor layer thereof is connected to a first driving control line wiring layer, and the second gate conductor layer thereof is connected to a word line wiring layer, and

the first driving control line wiring layer and the word line wiring layer are disposed parallel to a row direction (first invention).

In the first invention described above, the first driving control line wiring layer is shared among the semiconductor base materials adjacent to each other in a column direction (second invention).

In the first invention described above, a first peripheral length, in plan view, of the semiconductor base material covered by the first gate insulating layer is shorter than a second peripheral length, in plan view, of the semiconductor base material covered by the second gate insulating layer (third invention).

In the first invention described above, a first gate capacitance between the first gate conductor layer and the channel semiconductor layer is made larger than a second gate capacitance between the second gate conductor layer and the channel semiconductor layer (fourth invention).

In the first invention described above, in the write operation, a group of positive holes generated by an impact ionization phenomenon or by a gate-induced drain leakage current are retained inside the channel semiconductor layer, and a voltage of the channel semiconductor layer is made equal to a first data retention voltage that is higher than the voltage of either the first impurity layer or the second impurity layer or that is higher than the voltages of both the first impurity layer and the second impurity layer, and

in the erase operation, the voltages applied to the first impurity layer, the second impurity layer, the first gate conductor layer, and the second gate conductor layer are controlled to discharge the group of positive holes through either the first impurity layer or the second impurity layer or both the first impurity layer and the second impurity layer, and the voltage of the channel semiconductor layer is made equal to a second data retention voltage that is lower than the first data retention voltage (fifth invention).

BRIEF DESCRIPTION OF DRAWINGS

FIG. 1 is a structural diagram of a memory device including an SGT according to a first embodiment.

FIGS. 2A and 2B include diagrams for explaining an effect attained in a case where the gate capacitance of a first gate conductor layer 5 a connected to a plate line wiring layer PL is made larger than the gate capacitance of a second gate conductor layer 5 b to which a word line wiring layer WL is connected in the memory device including an SGT according to the first embodiment.

FIGS. 3AA, 3AB and 3AC include diagrams for explaining a mechanism of a write operation of the memory device including an SGT according to the first embodiment.

FIG. 3B includes diagrams for explaining the mechanism of the write operation of the memory device including an SGT according to the first embodiment.

FIG. 4A is a diagram for explaining a mechanism of a page erase operation of the memory device including an SGT according to the first embodiment.

FIGS. 4BA, 4BB, 4BC and 4BD include diagrams for explaining the mechanism of the page erase operation of the memory device including an SGT according to the first embodiment.

FIG. 4C includes diagrams for explaining the mechanism of the page erase operation of the memory device including an SGT according to the first embodiment.

FIGS. 4DA, 4DB, 4DC and 4DD include diagrams for explaining a mechanism of the page erase operation of the memory device including an SGT according to the first embodiment.

FIGS. 5AA, 5AB and 5AC include diagrams for explaining an arrangement structure of a source line wiring layer, a plate line wiring layer, a word line wiring layer, and a bit line wiring layer of the memory device including an SGT according to the first embodiment.

FIGS. 5BA, 5BB and 5BC include diagrams for explaining an arrangement structure of the source line wiring layer, the plate line wiring layer, the word line wiring layer, and the bit line wiring layer of the memory device including an SGT according to the first embodiment.

FIGS. 5CA and 5CB include band diagrams for explaining a region in which a group of positive holes are present in a case where the memory device including an SGT according to the first embodiment is miniaturized.

FIG. 5D is a band diagram for explaining a region in which a group of positive holes are present in the case where the memory device including an SGT according to the first embodiment is miniaturized.

FIGS. 6A, 6B and 6C include diagrams for explaining a mechanism of a read operation of the memory device including an SGT according to the first embodiment.

FIGS. 7A, 7B, 7C and 7D include diagrams for explaining a write operation of a DRAM memory cell including no capacitor in the related art.

FIGS. 8A and 8B include diagrams for explaining a problem in the operation of the DRAM memory cell including no capacitor in the related art.

FIGS. 9A, 9B, and 9C include diagrams for explaining a read operation of the DRAM memory cell including no capacitor in the related art.

DESCRIPTION OF EMBODIMENTS

Hereinafter, embodiments of a memory device (hereinafter called a dynamic flash memory) including a semiconductor element according to the present invention will be described with reference to the drawings.

First Embodiment

The structure and operation mechanisms of a dynamic flash memory cell according to a first embodiment of the present invention will be described with reference to FIG. 1 to FIGS. 6A-6C. The structure of the dynamic flash memory cell will be described with reference to FIG. 1. An effect attained in a case where the gate capacitance of a first gate conductor layer 5 a connected to a plate line wiring layer PL is made larger than the gate capacitance of a second gate conductor layer 5 b to which a word line wiring layer WL is connected will be described with reference to FIGS. 2A and 2B. A mechanism of a data write operation will be described with reference to FIGS. 3AA-3AC and FIG. 3B, mechanisms of a data erase operation will be described with reference to FIG. 4A to FIGS. 4DA-4DD, and a mechanism of a data read operation will be described with reference to FIGS. 6A-6C.

FIG. 1 illustrates the structure of the dynamic flash memory cell according to the first embodiment of the present invention. On the top and the bottom of a silicon semiconductor pillar 2 (hereinafter, the silicon semiconductor pillar is referred to as “Si pillar”) (which is an example of “semiconductor base material” in the claims) of the P or i (intrinsic) conductivity type formed on a substrate (which is an example of “substrate” in the claims), N⁺ layers 3 a and 3 b (which are examples of “first impurity layer” and “second impurity layer” in the claims), one of which functions as the source and the other functions as the drain, are formed respectively. The part of the Si pillar 2 between the N⁺ layers 3 a and 3 b that function as the source and the drain functions as a channel region 7 (which is an example of “channel semiconductor layer” in the claims). A first gate insulating layer 4 a (which is an example of “first gate insulating layer” in the claims) is formed so as to surround about one-half of the entire periphery of the side surface of the channel region 7, and a second gate insulating layer 4 b (which is an example of “second gate insulating layer” in the claims) is formed so as to surround the entire periphery of the side surface of the channel region 7. The first gate insulating layer 4 a and the second gate insulating layer 4 b are in contact with or in close vicinity to the N⁺ layers 3 a and 3 b that function as the source and the drain respectively. Around the first gate insulating layer 4 a and the second gate insulating layer 4 b, the first gate conductor layer 5 a (which is an example of “first gate conductor layer” in the claims) and the second gate conductor layer 5 b (which is an example of “second gate conductor layer” in the claims) are formed respectively. The first gate conductor layer 5 a surrounds about one-half of the entire periphery of the side surface of the channel region 7 in a pillar form with the first gate insulating layer 4 a therebetween. The first gate conductor layer 5 a and the second gate conductor layer 5 b are isolated from each other by an insulating layer 6 (which is also referred to as “first insulating layer”). The channel region 7 between the N⁺ layers 3 a and 3 b is constituted by a first channel Si layer 7 a (which is also referred to as “first channel semiconductor layer”) surrounded by the first gate insulating layer 4 a and a second channel Si layer 7 b (which is also referred to as “second channel semiconductor layer”) surrounded by the second gate insulating layer 4 b. Accordingly, the N⁺ layers 3 a and 3 b that function as the source and the drain, the channel region 7, the first gate insulating layer 4 a, the second gate insulating layer 4 b, the first gate conductor layer 5 a, and the second gate conductor layer 5 b constitute a dynamic flash memory cell 10. The N⁺ layer 3 a that functions as the source is connected to a source line wiring layer SL (which is an example of “source line wiring layer” in the claims), the N⁺ layer 3 b that functions as the drain is connected to a bit line wiring layer BL (which is an example of “bit line wiring layer” in the claims), the first gate conductor layer 5 a is connected to the plate line wiring layer PL (which is an example of “first driving control line wiring layer” in the claims), and the second gate conductor layer 5 b is connected to the word line wiring layer WL (which is an example of “word line wiring layer” in the claims). Desirably, the structure is such that the gate capacitance of the first gate conductor layer 5 a to which the plate line wiring layer PL is connected is larger than the gate capacitance of the second gate conductor layer 5 b to which the word line wiring layer WL is connected.

Although the first gate insulating layer 4 a surrounds about one-half of the side surface of the Si pillar 2 in FIG. 1, and therefore, a first peripheral length (which is an example of “first peripheral length” in the claims), in plan view, of the Si pillar 2 covered by the first gate insulating layer 4 a is shorter than a second peripheral length (which is an example of “second peripheral length” in the claims), in plan view, of the second gate insulating layer 4 b that surrounds the entire periphery of the side surface of the Si pillar 2, the first gate insulating layer 4 a may be formed so as to surround the entire periphery of the side surface of the Si pillar 2 to make the first and second peripheral lengths be the same lengths.

In FIG. 1, to make the gate capacitance of the first gate conductor layer 5 a connected to the plate line wiring layer PL larger than the gate capacitance of the second gate conductor layer 5 b to which the word line wiring layer WL is connected, the gate length of the first gate conductor layer 5 a is made longer than the gate length of the second gate conductor layer 5 b. Alternatively, instead of making the gate length of the first gate conductor layer 5 a longer than the gate length of the second gate conductor layer 5 b, the thicknesses of the respective gate insulating layers may be made different such that the thickness of the gate insulating film of the first gate insulating layer 4 a is thinner than the thickness of the gate insulating film of the second gate insulating layer 4 b. Alternatively, the dielectric constants of the materials of the respective gate insulating layers may be made different such that the dielectric constant of the gate insulating film of the first gate insulating layer 4 a is higher than the dielectric constant of the gate insulating film of the second gate insulating layer 4 b. The gate capacitance of the first gate conductor layer 5 a connected to the plate line wiring layer PL may be made larger than the gate capacitance of the second gate conductor layer 5 b to which the word line wiring layer WL is connected, by a combination of any of the lengths of the gate conductor layers 5 a and 5 b and the thicknesses and dielectric constants of the gate insulating layers 4 a and 4 b.

FIGS. 2A and 2B are diagrams for explaining an effect attained in a case where the gate capacitance of the first gate conductor layer 5 a connected to the plate line wiring layer PL is made larger than the gate capacitance of the second gate conductor layer 5 b to which the word line wiring layer WL is connected.

FIG. 2A is a diagram for explaining the capacitance relationships of the respective lines. The capacitance C_(FB) of the channel region 7 is equal to the sum of the capacitance C_(WL) between the gate conductor layer 5 b to which the word line wiring layer WL is connected and the channel region 7, the capacitance C_(PL) between the gate conductor layer 5 a to which the plate line wiring layer PL is connected and the channel region 7, the junction capacitance C_(SL) of the PN junction between the source N⁺ layer 3 a to which the source line wiring layer SL is connected and the channel region 7, and the junction capacitance C_(BL) of the PN junction between the drain N⁺ layer 3 b to which the bit line wiring layer BL is connected and the channel region 7, and is expressed as follows.

C _(FB) =C _(WL) +C _(PL) +C _(BL) +C _(SL)  (1)

Therefore, the coupling ratio β_(WL) between the word line wiring layer WL and the channel region 7, the coupling ratio β_(PL) between the plate line wiring layer PL and the channel region 7, the coupling ratio β_(BL) between the bit line wiring layer BL and the channel region 7, and the coupling ratio β_(SL) between the source line wiring layer SL and the channel region 7 are expressed as follows.

β_(WL) =C _(WL)/(C _(WL) +C _(PL) +C _(BL) +C _(SL))  (2)

β_(PL) =C _(PL)/(C _(WL) +C _(PL) +C _(BL) +C _(SL))  (3)

β_(BL) =C _(BL)/(C _(WL) +C _(PL) +C _(BL) +C _(SL))  (4)

β_(SL) =C _(SL)/(C _(WL) +C _(PL) +C _(BL) +C _(SL))  (5)

Here, C_(PL)>C_(WL) holds, and therefore, this results in β_(PL)>β_(WL).

FIG. 2B is a diagram for explaining a change in the voltage V_(FB) of the channel region 7 when the voltage V_(WL) of the word line wiring layer WL rises at the time of a read operation or a write operation and subsequently drops. Here, the potential difference ΔV_(FB) when the voltage V_(WL) of the word line wiring layer WL rises from 0 V to a high voltage state V_(WLH) and the voltage V_(FB) of the channel region 7 transitions from a low voltage state V_(FBL) to a high voltage state V_(FBH) is expressed as follows.

$\begin{matrix} {{\Delta V_{FB}} = {{V_{{FB}H} - V_{{FB}L}} = {\beta_{WL} \times V_{WLH}}}} & (6) \end{matrix}$

The coupling ratio β_(WL) between the word line wiring layer WL and the channel region 7 is small and the coupling ratio β_(PL) between the plate line wiring layer PL and the channel region 7 is large, and therefore, ΔV_(FB) is small, and the voltage V_(FB) of the channel region 7 negligibly changes even when the voltage V_(WL) of the word line wiring layer WL changes at the time of a read operation or a write operation.

FIGS. 3AA to 3AC and FIG. 3B illustrate a write operation (which is an example of “write operation” in the claims) of the dynamic flash memory cell according to the first embodiment of the present invention. FIG. 3AA illustrates a mechanism of the write operation, and FIG. 3AB illustrates operation waveforms of the bit line wiring layer BL, the source line wiring layer SL, the plate line wiring layer PL, the word line wiring layer WL, and the channel region 7 that functions as a floating body FB. At time T0, the dynamic flash memory cell is in a “0” erase state, and the voltage of the channel region 7 is equal to V_(FB)“0”. Vss is applied to the bit line wiring layer BL, the source line wiring layer SL, and the word line wiring layer WL, and V_(PLL) is applied to the plate line wiring layer PL. Here, for example, Vss is equal to 0 V and V_(PLL) is equal to 2 V. Subsequently, from time T1 to time T2, when the bit line wiring layer BL rises from Vss to V_(BLH), in a case where, for example, Vss is equal to 0 V, the voltage of the channel region 7 becomes equal to V_(FB)“0”+_(BL)×V_(BLH) due to capacitive coupling between the bit line wiring layer BL and the channel region 7.

The description of the write operation of the dynamic flash memory cell will be continued with reference to FIGS. 3AA and 3AB. From time T3 to time T4, the word line wiring layer WL rises from Vss to V_(WLH). Accordingly, when the threshold voltage for “0” erase for a second N-channel MOS transistor region that is a region in which the second gate conductor layer 5 b to which the word line wiring layer WL is connected surrounds the channel region 7 b is denoted by Vt_(WL)“0”, as the voltage of the word line wiring layer WL rises, in a range from Vss to Vt_(WL)“0”, the voltage of the channel region 7 becomes equal to V_(FB)“0”+β_(BL)×V_(BLH)+β_(WL)×Vt_(WL)“0” due to second capacitive coupling between the word line wiring layer WL and the channel region 7. When the voltage of the word line wiring layer WL rises to Vt_(WL)“0” or above, an inversion layer 12 b in a ring form is formed in the channel region 7 on the inner periphery of the second gate conductor layer 5 b and interrupts the second capacitive coupling between the word line wiring layer WL and the channel region 7.

The description of the write operation of the dynamic flash memory cell will be continued with reference to FIGS. 3AA and 3AB. From time T3 to time T4, for example, a fixed voltage V_(PLL)=2 V is applied to the first gate conductor layer 5 a to which the plate line wiring layer PL is connected, and the second gate conductor layer 5 b to which the word line wiring layer WL is connected is increased to, for example, V_(WLH)=4 V. As a result, as illustrated in FIG. 3AA, an inversion layer 12 a is formed in a part along the gate conductor layer 5 a in the channel region 7 on the inner periphery of the first gate conductor layer 5 a to which the plate line wiring layer PL is connected, and a pinch-off point 13 is present in the inversion layer 12 a. As a result, a first N-channel MOS transistor region formed of the channel region 7 a that is surrounded by the first gate conductor layer 5 a operates in the saturation region. In contrast, the second N-channel MOS transistor region including the second gate conductor layer 5 b to which the word line wiring layer WL is connected operates in the linear region. As a result, a pinch-off point is not present in the channel region 7 on the inner periphery of the second gate conductor layer 5 b to which the word line wiring layer WL is connected, and the inversion layer 12 b is formed on the entire inner periphery of the gate conductor layer 5 b. The inversion layer 12 b that is formed on the entire inner periphery of the second gate conductor layer 5 b to which the word line wiring layer WL is connected substantially functions as the drain of the first N-channel MOS transistor region. As a result, the electric field becomes maximum in a first boundary region of the channel region 7 between the first N-channel MOS transistor region including the first gate conductor layer 5 a and the second N-channel MOS transistor region including the second gate conductor layer 5 b that are connected in series, and an impact ionization phenomenon occurs in this region. This region is a source-side region when viewed from the second N-channel MOS transistor region including the second gate conductor layer 5 b to which the word line wiring layer WL is connected, and therefore, this phenomenon is called a source-side impact ionization phenomenon. By this source-side impact ionization phenomenon, electrons flow from the N⁺ layer 3 a to which the source line wiring layer SL is connected toward the N⁺ layer 3 b to which the bit line wiring layer BL is connected. The accelerated electrons collide with lattice Si atoms, and electron-positive hole pairs are generated by the kinetic energy. Although some of the generated electrons flow into the first gate conductor layer 5 a and into the second gate conductor layer 5 b, most of the generated electrons flow into the N⁺ layer 3 b to which the bit line wiring layer BL is connected (not illustrated).

As illustrated in FIG. 3AC, a generated group of positive holes 9 (which is an example of “group of positive holes” in the claims) are majority carriers in the channel region 7, with which the channel region 7 is charged to a positive bias. The N⁺ layer 3 a to which the source line wiring layer SL is connected is at 0 V, and therefore, the channel region 7 is charged up to the built-in voltage Vb (about 0.7 V) of the PN junction between the N⁺ layer 3 a to which the source line wiring layer SL is connected and the channel region 7. When the channel region 7 is charged to a positive bias, the threshold voltages for the first N-channel MOS transistor region and the second N-channel MOS transistor region decrease due to a substrate bias effect.

The description of the write operation of the dynamic flash memory cell will be continued with reference to FIG. 3AB. From time T6 to time T7, the voltage of the word line wiring layer WL drops from V_(WLH) to Vss. During this period, although the second capacitive coupling is formed between the word line wiring layer WL and the channel region 7, the inversion layer 12 b interrupts the second capacitive coupling until the voltage of the word line wiring layer WL drops from V_(WLH) to a threshold voltage Vt_(WL)“1” for the second N-channel MOS transistor region or below when the voltage of the channel region 7 is equal to Vb. Therefore, the capacitive coupling between the word line wiring layer WL and the channel region 7 is substantially formed only during a period from when the word line wiring layer WL drops to Vt_(WL)“1” or below to when the word line wiring layer WL drops to Vss. As a result, the voltage of the channel region 7 becomes equal to Vb−β_(WL)×Vt_(WL)“1”. Here, Vt_(WL)“1” is lower than Vt_(WL)“0” described above, and β_(WL)×Vt_(WL)“1” is small.

The description of the write operation of the dynamic flash memory cell will be continued with reference to FIG. 3AB. From time T8 to time T9, the bit line wiring layer BL drops from V_(BLH) to Vss. The bit line wiring layer BL and the channel region 7 are capacitively coupled with each other, and therefore, the “1” write voltage V_(FB)“1” of the channel region 7 becomes as follows at the end.

V _(FB)“1”=Vb−β _(WL) ×Vt _(WL)“1”−β_(BL) ×V _(BLH)  (7)

Here, the coupling ratio β_(BL) between the bit line wiring layer BL and the channel region 7 is also small. Accordingly, as illustrated in FIG. 3B, the threshold voltage for the second N-channel MOS transistor region of the second channel region 7 b to which the word line wiring layer WL is connected decreases. The page write operation in which the voltage V_(FB)“1” in the “1” write state of the channel region 7 is assumed to be a first data retention voltage (which is an example of “first data retention voltage” in the claims) is performed to assign logical storage data “1”.

At the time of the write operation, electron-positive hole pairs may be generated by an impact ionization phenomenon in a second boundary region between the first impurity layer 3 a and the first channel semiconductor layer 7 a or in a third boundary region between the second impurity layer 3 b and the second channel semiconductor layer 7 b instead of the first boundary region, and the channel region 7 may be charged with the generated group of positive holes 9.

A mechanism of an erase operation (which is an example of “erase operation” in the claims) will be described with reference to FIG. 4A to FIGS. 4DA-4DD.

FIG. 4A is a memory block circuit diagram for explaining a page erase operation. Although nine memory cells CL₁₁ to CL₃₃ in three rows and three columns are illustrated, the actual memory is larger than this matrix.

When memory cells are arranged in a matrix, one of the directions of the arrangement is called a row direction (or in rows) and the direction perpendicular to the one of the directions is called “column direction” (or in columns). To each of the memory cells, the source line wiring layer SL, a corresponding one of the bit line wiring layers BL₁ to BL₃, a corresponding one of the plate line wiring layers PL₁ to PL₃, and a corresponding one of the word line wiring layers WL₁ to WL₃ are connected. For example, it is assumed that memory cells CL₂₁ to CL₂₃ to which the plate line wiring layer PL₂ and the word line wiring layer WL₂ are connected are selected in this block and a page erase operation is performed.

A mechanism of the page erase operation will be described with reference to FIGS. 4BA to 4BD and FIG. 4C. Here, the channel region 7 between the N⁺ layers 3 a and 3 b is electrically isolated from the substrate and functions as a floating body. FIG. 4BA is a timing operation waveform diagram of main nodes in the erase operation. In FIG. 4BA, T0 to T12 indicate times from the start to the end of the erase operation. FIG. 4BB illustrates a state at time T0 before the erase operation, in which the group of positive holes 9 generated by impact ionization in the previous cycle are stored in the channel region 7. From time T1 to time T2, the bit line wiring layers BL₁ to BL₃ and the source line wiring layer SL rise from Vss to V_(BLH) and V_(SLH) respectively and are in a high-voltage state. Here, Vss is, for example, equal to 0 V. With this operation, during the subsequent period, namely, a first period from time T3 to time T4, the plate line wiring layer PL₂ selected in the page erase operation rises from a first voltage V_(PLL) to a second voltage V_(PLH) and is in a high-voltage state, the word line wiring layer WL₂ selected in the page erase operation rises from a third voltage Vss to a fourth voltage V_(WLH) and is in a high-voltage state, and this prevents the inversion layer 12 a on the inner periphery of the first gate conductor layer 5 a to which the plate line wiring layer PL₂ is connected and the inversion layer 12 b on the inner periphery of the second gate conductor layer 5 b to which the word line wiring layer WL₂ is connected from being formed in the channel region 7. Therefore, when the threshold voltage for the second N-channel MOS transistor region on the side of the word line wiring layer WL₂ and the threshold voltage for the first N-channel MOS transistor region on the side of the plate line wiring layer PL₂ are denoted by Vt_(WL) and Vt_(PL) respectively, it is desirable that the voltages V_(BLH) and V_(SLH) satisfy V_(BLH)>V_(WLH)+V_(tWL) and V_(SLH)>V_(PLH)+V_(tPL). For example, in a case where Vt_(WL) and V_(tPL) are equal to 0.5 V, V_(WLH) and V_(PLH) need to be set to 3 V, and V_(BLH) and V_(SLH) need to be set to 3.5 V or higher.

The description of the mechanism of the page erase operation illustrated in FIG. 4BA will be continued. As the plate line wiring layer PL₂ and the word line wiring layer WL₂ respectively rise to the second voltage V_(PLH) and the fourth voltage V_(WLH) and are in a high-voltage state during the first period from time T3 to time T4, the voltage of the channel region 7 in a floating state is increased due to first capacitive coupling between the plate line wiring layer PL₂ and the channel region 7 and the second capacitive coupling between the word line wiring layer WL₂ and the channel region 7. The voltage of the channel region 7 rises from V_(FB)“1” in the “1” write state to a high voltage. This voltage rise is possible because the voltage of the bit line wiring layers BL₁ to BL₃ and that of the source line wiring layer SL are high voltages of V_(BL) and V_(SL) respectively and the PN junction between the source N⁺ layer 3 a and the channel region 7 and the PN junction between the drain N⁺ layer 3 b and the channel region 7 are in a reverse bias state accordingly.

The description of the mechanism of the page erase operation illustrated in FIG. 4BA will be continued. During the subsequent period, namely, a second period from time T5 to time T6, the voltage of the bit line wiring layers BL₁ to BL₃ and that of the source line wiring layer SL respectively drop from high voltages of V_(BL) and V_(SL) to Vss. As a result, the PN junction between the source N⁺ layer 3 a and the channel region 7 and the PN junction between the drain N⁺ layer 3 b and the channel region 7 are in a forward bias state as illustrated in FIG. 4BC, and a remaining group of positive holes among the group of positive holes 9 in the channel region 7 are discharged to the source N⁺ layer 3 a and to the drain N⁺ layer 3 b. As a result, the voltage V_(FB) of the channel region 7 becomes equal to the built-in voltage Vb of the PN junction formed by the source N⁺ layer 3 a and the P layer, namely, the channel region 7, and the PN junction formed by the drain N⁺ layer 3 b and the P layer, namely, the channel region 7.

The description of the mechanism of the page erase operation illustrated in FIG. 4BA will be continued. Subsequently, from time T7 to time T8, the voltage of the bit line wiring layers BL₁ to BL₃ and that of the source line wiring layer SL rise from Vss to high voltages of V_(BLH) and V_(SL)H respectively. With this operation, as illustrated in FIG. 4BD, when the plate line wiring layer PL₂ drops from the second voltage V_(PL)H to the first voltage V_(PLL) and the word line wiring layer WL₂ drops from the fourth voltage V_(WLH) to the third voltage Vss during a third period from time T9 to time T10, the voltage V_(FB) of the channel region 7 efficiently changes from Vb to V_(FB)“0” due to the first capacitive coupling between the plate line wiring layer PL₂ and the channel region 7 and the second capacitive coupling between the word line wiring layer WL₂ and the channel region 7 without the inversion layer 12 a on the side of the plate line wiring layer PL₂ or the inversion layer 12 b on the side of the word line wiring layer WL₂ being formed in the channel region 7. The voltage difference ΔV_(FB) of the channel region 7 between the “1” write state and the “0” erase state is expressed by the following expressions.

$\begin{matrix} {{V_{FB}{\,^{‶}1^{''}}} = {{Vb} - {\beta_{WL} \times {Vt}_{WL}{\,^{‶}1^{''}}} - {\beta_{BL} \times V_{BLH}}}} & (7) \end{matrix}$ $\begin{matrix} {{V_{FB}{\,^{‶}0^{''}}} = {{Vb} - {\beta_{WL} \times V_{WLH}} - {\beta_{PL} \times \left( {V_{PLH} - V_{PLL}} \right)}}} & (8) \end{matrix}$ $\begin{matrix} \begin{matrix} {{\Delta V_{FB}} = {{V_{FB}{\,^{‶}1^{''}}} - {V_{FB}{\,^{‶}0^{''}}}}} \\ {= {{\beta_{WL} \times V_{WLH}} + {\beta_{PL} \times \left( {V_{PLH} - V_{PLL}} \right)} -}} \\ {{\beta_{WL} \times {Vt}_{WL}{\,^{‶}1^{''}}} - {\beta_{BL} \times V_{BLH}}} \end{matrix} & (9) \end{matrix}$

Here, the sum of W_(L) and R_(PL) is greater than or equal to 0.8, ΔV_(FB) is large, and a sufficient margin is provided.

As a result, as illustrated in FIG. 4C, a large margin is provided between the “1” write state and the “0” erase state. Here, in the “0” erase state, the threshold voltage on the side of the plate line wiring layer PL₂ is high due to a substrate bias effect. Therefore, when the voltage applied to the plate line wiring layer PL₂ is set to, for example, the threshold voltage or lower, the first N-channel MOS transistor region on the side of the plate line wiring layer PL₂ becomes non-conducting and does not allow the memory cell current to flow therethrough. This state is illustrated.

The description of the mechanism of the page erase operation illustrated in FIG. 4BA will be continued. During the subsequent period, namely, a fourth period from time T11 to time T12, the voltage of the bit line wiring layers BL₁ to BL₃ drops from V_(BLH) to Vss and that of the source line wiring layer SL drops from V_(SLH) to Vss, and the erase operation ends. At this time, although the bit line wiring layers BL₁ to BL₃ and the source line wiring layer SL slightly decrease the voltage of the channel region 7 due to capacitive coupling, this decrease is equal to the increase in the voltage of the channel region 7 by the bit line wiring layers BL₁ to BL₃ and the source line wiring layer SL due to capacitive coupling from time T7 to time T8, and therefore, the decrease and the increase in the voltage by the bit line wiring layers BL₁ to BL₃ and the source line wiring layer SL are canceled out, and the voltage of the channel region 7 is not affected consequently. The page erase operation in which the voltage V_(FB)“0” in the “0” erase state of the channel region 7 is assumed to be a second data retention voltage (which is an example of “second data retention voltage” in the claims) is performed to assign logical storage data “0”.

Now, a mechanism of the page erase operation will be described with reference to FIGS. 4DA to 4DD. FIGS. 4DA-4DD are different from FIGS. 4BA-4BD in that the source line wiring layer SL is kept at Vss or put in a floating state and the plate line wiring layer PL₂ is kept at Vss during the page erase operation. Accordingly, from time T1 to time T2, even when the bit line wiring layers BL₁ to BL₃ rise from Vss to V_(BLH), the first N-channel MOS transistor region of the plate line wiring layer PL₂ is non-conducting, and the memory cell current does not flow therethrough. Therefore, the group of positive holes 9 caused by an impact ionization phenomenon are not generated. The others are the same as in FIGS. 4BA-4BD, and the bit line wiring layers BL₁ to BL₃ change between Vss and V_(BLH), and the word line wiring layer WL₂ changes between Vss and V_(WLH). As a result, as illustrated in FIG. 4DC, the group of positive holes 9 are discharged to the second impurity layer, namely, the N⁺ layer 3 b, of the bit line wiring layers BL₁ to BL₃.

FIGS. 5AA-5AC and FIGS. 5BA-5BC include diagrams for explaining an arrangement structure of the source line wiring layer, the plate line wiring layer, the word line wiring layer, and the bit line wiring layer of the memory device including an SGT according to the first embodiment of the present invention.

FIG. 5AA is a plan view of a part of a memory cell block, FIG. 5AB is a cross-sectional view cut along line X-X′ in FIG. 5AA, and FIG. 5AC is a cross-sectional view cut along line Y-Y′ in FIG. 5AA. FIGS. 5AA-5AC illustrate a semiconductor substrate 50, which is a P layer, and a first impurity layer 51, which is an N⁺ layer that functions as the source line wiring layer SL. On the semiconductor substrate 50, a P layer 53, which is a channel layer, and a second impurity layer 54 are formed in the vertical direction. In upper layers above the source line wiring layer SL 51, a plate line wiring layer PL 56 and a word line wiring layer WL 57 are disposed parallel to the row direction (which is an example of “row direction” in the claims. In a further upper layer, a bit line wiring layer BL 58 is disposed in the column direction (which is an example of “column direction” in the claim).

As illustrated in FIGS. 5AA-5AC, the plate line wiring layer PL 56 surrounds about one-half of the entire periphery of the side surface of the channel-layer P layer 53 with the gate insulating layer therebetween. That is, the part of the plate line wiring layer PL 56 that surrounds the channel-layer P layer 53 assumes the roles of the first gate conductor layer 5 a. The word line wiring layer WL 57 surrounds the entire side surface of the channel-layer P layer 53 with the gate insulating layer therebetween. The part of the word line wiring layer WL 57 that surrounds the channel-layer P layer 53 assumes the roles of the second gate conductor layer 5 b. The same applies to FIGS. 5BA-5BC described below.

Note that the semiconductor substrate 50 may be an SOI substrate or may be a substrate formed of a P-layer substrate in which a well layer is provided.

FIGS. 5BA to 5BC illustrate an example in which the plate line wiring layer is disposed so as to be shared among the Si pillars 2 in two rows adjacent to each other in the column direction in addition to the plurality of Si pillars 2 in the row direction as illustrated in FIG. 5AA-5AC. FIG. 5BA is a plan view of a part of a memory cell block, FIG. 5BB is a cross-sectional view cut along line X-X′ in FIG. 5BA, and FIG. 5BC is a cross-sectional view cut along line Y-Y′ in FIG. 5BA.

When the plate line wiring layer is disposed so as to be shared among the Si pillars 2 adjacent to each other in the column direction, the design rule of the plate line wiring layer can be relaxed, and from the viewpoint of processes, the plate line wiring layer and the word line wiring layer in an upper layer above the plate line wiring layer can be easily processed.

FIGS. 5CA-5CB and FIG. 5D include band diagrams for explaining a region in which a group of positive holes are present in a case where the memory device including an SGT according to the first embodiment is miniaturized.

FIG. 5CA illustrates an example in which the diameter of the Si pillar 2 is large, and FIG. 5CB illustrates an example in which the diameter of the Si pillar 2 is small. To write “1”, a group of positive holes generated by an impact ionization phenomenon or by a gate-induced drain leakage current are stored inside the Si pillar 2. As illustrated in FIG. 5CB, as the diameter of the Si pillar 2 is made smaller, a space in the channel-layer P layer 53 in which the group of positive holes are stored becomes narrower.

FIG. 5D is a band diagram illustrating an example in which about one-half of the entire periphery of the side surface of the channel-layer P layer 53 is surrounded by the plate line wiring layer PL. With this, even when the diameter of the Si pillar 2 is made smaller, an electric field is applied to the channel-layer P layer 53 not circumferentially to the entire surface but in one direction, and therefore, a region in which the group of positive holes are present can be provided.

FIGS. 6A to 6C are diagrams for explaining a read operation of the dynamic flash memory cell according to the first embodiment of the present invention. As illustrated in FIG. 6A, when the channel region 7 is charged up to the built-in voltage Vb (about 0.7 V), the threshold voltage for the second N-channel MOS transistor region including the second gate conductor layer 5 b to which the word line wiring layer WL is connected decreases due to a substrate bias effect. This state is assigned to logical storage data “1”. As illustrated in FIG. 6B, a memory block selected before writing is in an erase state “0” in advance, and the voltage V_(FB) of the channel region 7 is equal to V_(FB)“0”. With a write operation, a write state “1” is stored at random. As a result, logical storage data of logical “0” and that of logical “1” are created for the word line wiring layer WL. As illustrated in FIG. 6C, the level difference between the two threshold voltages of the word line wiring layer WL is used to perform reading by a sense amplifier. When the voltage applied to the first gate conductor layer 5 a connected to the plate line wiring layer PL is set to a voltage higher than the threshold voltage at the time of logical storage data “1” and lower than the threshold voltage at the time of logical storage data “0” in data reading, a property that a current does not flow even when the voltage of the word line wiring layer WL is increased can be attained as illustrated in FIG. 6C.

Regardless of whether the horizontal cross-sectional shape of the Si pillar 2 illustrated in FIG. 1 is a round shape, an elliptic shape, or a rectangular shape, the operations of the dynamic flash memory described in this embodiment can be performed. Further, a dynamic flash memory cell having a round shape, a dynamic flash memory cell having an elliptic shape, and a dynamic flash memory cell having a rectangular shape may coexist on the same chip.

With reference to FIG. 1, the dynamic flash memory element including an example SGT that includes the first gate conductor layer 5 a surrounding about one-half of the entire periphery of the side surface of the Si pillar 2 and the second gate conductor layer 5 b surrounding the entire periphery of the side surface of the Si pillar 2 has been described. As illustrated in the description of this embodiment, the dynamic flash memory element needs to have a structure that satisfies the condition that the group of positive holes 9 generated by an impact ionization phenomenon are retained in the channel region 7. For this, the channel region 7 needs to have a floating body structure isolated from the substrate. Alternatively, the dynamic flash memory element may have a device structure using SOI (Silicon On Insulator) (see, for example, NPL 7 to NPL 11). In this device structure, the bottom portion of the channel region is in contact with an insulating layer of the SOI substrate, and the other portion of the channel region is surrounded by a gate insulating layer and an element isolation insulating layer. Also with such a structure, the channel region has a floating body structure. Accordingly, the dynamic flash memory element provided in this embodiment needs to satisfy the condition that the channel region has a floating body structure.

To write “1”, electron-positive hole pairs may be generated by using a gate-induced drain leakage (GIDL) current (see for example, NPL 11), and the channel region 7 may be filled with the generated group of positive holes.

Expressions (1) to (12) provided in the specification and in the drawings are expressions used to qualitatively explain the phenomena, and are not intended to limit the phenomena.

Although the reset voltages of the word line wiring layer WL, the bit line wiring layer BL, and the source line wiring layer SL are specified as Vss in the explanations of FIGS. 3AA-3AC and FIG. 3B, the reset voltages may be set to different voltages.

Although FIGS. 4BA-4BD and FIGS. 4DA-4DD illustrate example conditions of the page erase operation, the voltages applied to the source line wiring layer SL, the plate line wiring layer PL, the bit line wiring layer BL, and the word line wiring layer WL may be changed as long as a state in which the group of positive holes 9 in the channel region 7 are discharged through either the N⁺ layer 3 a or the N⁺ layer 3 b or both the N⁺ layer 3 a and the N⁺ layer 3 b can be attained. Further, in the page erase operation, a voltage may be applied to the source line wiring layer SL of a selected page, and the bit line wiring layer BL may be put in a floating state. In the page erase operation, a voltage may be applied to the bit line wiring layer BL of a selected page, and the source line wiring layer SL may be put in a floating state.

In FIG. 1, in the vertical direction, in a part of the channel region 7 surrounded by the insulating layer 6 that is the first insulating layer, the potential distribution of the first channel region 7 a and that of the second channel region 7 b are connected and formed. Accordingly, the first channel region 7 a and the second channel region 7 b that constitute the channel region 7 are connected in the vertical direction in the region surrounded by the insulating layer 6 that is the first insulating layer.

Note that in FIG. 1, it is desirable to make the length of the first gate conductor layer 5 a, in the vertical direction, to which the plate line wiring layer PL is connected further longer than the length of the second gate conductor layer 5 b, in the vertical direction, to which the word line wiring layer WL is connected to attain C_(PL)>C_(WL). However, when only the plate line wiring layer PL is added, the coupling ratio (C_(WL)/(C_(PL)+C_(WL)+C_(BL)+C_(SL))), of capacitive coupling, of the word line wiring layer WL to the channel region 7 decreases. As a result, the potential change ΔV_(FB) of the floating body, namely, the channel region 7, decreases.

As the voltage V_(PLL) of the plate line wiring layer PL, for example, another fixed voltage may be applied in operation modes other than a mode in which selective erasing is performed in a block erase operation.

Although the channel region 7 a is entirely surrounded by the first gate conductor layer 5 a in FIG. 1, the first gate conductor layer 5 a may be divided into two or more gate conductor layers, and each of the gate conductor layers may function as a conductive electrode of the plate line wiring layer and surround the channel region 7 a. The two or more gate conductor layers obtained as a result of division may be operated synchronously or asynchronously at the same driving voltage or different driving voltages. Similarly, the second gate conductor layer 5 b may be divided into two or more gate conductor layers, and the gate conductor layers may each function as a conductive electrode of the word line wiring layer and may be operated synchronously or asynchronously at the same driving voltage or different driving voltages. Also in this case, the operations of the dynamic flash memory can be performed. In a case where the first gate conductor layer 5 a is divided into two or more gate conductor layers, at least one of the first gate conductor layers obtained as a result of division assumes the roles of the first gate conductor layer 5 a described above. In a case where the second gate conductor layer 5 b is divided into two or more gate conductor layers, at least one of the second gate conductor layers obtained as a result of division assumes the roles of the second gate conductor layer 5 b described above.

In FIG. 1, the position of the first gate conductor layer 5 a to which the plate line wiring layer PL is connected may be shifted upward in the vertical direction toward the second impurity layer 3 b, and the position of the second gate conductor layer 5 b to which the word line wiring layer WL is connected may be shifted downward in the vertical direction toward the first impurity layer 3 a. Also with this, the operations of the dynamic flash memory can be performed.

The above-described conditions of voltages applied to the bit line wiring layer BL, the source line wiring layer SL, the word line wiring layer WL, and the plate line wiring layer PL and the voltage of the floating body are examples for performing basic operations including the erase operation, the write operation, and the read operation, and other voltage conditions may be employed as long as basic operations of the present invention can be performed.

This embodiment has the following features.

(Feature 1)

The dynamic flash memory cell of this embodiment is constituted by the N⁺ layers 3 a and 3 b that function as the source and the drain, the channel region 7, the first gate insulating layer 4 a, the second gate insulating layer 4 b, the first gate conductor layer 5 a, and the second gate conductor layer 5 b, which are formed in a pillar form as a whole. The N⁺ layer 3 a that functions as the source is connected to the source line wiring layer SL, the N⁺ layer 3 b that functions as the drain is connected to the bit line wiring layer BL, the first gate conductor layer 5 a is connected to the plate line wiring layer PL, and the second gate conductor layer 5 b is connected to the word line wiring layer WL. A structure is employed in which the gate capacitance of the first gate conductor layer 5 a to which the plate line wiring layer PL is connected is larger than the gate capacitance of the second gate conductor layer 5 b to which the word line wiring layer WL is connected, which is a feature. In the dynamic flash memory cell, the first gate conductor layer and the second gate conductor layer are stacked in the vertical direction. Accordingly, even when the structure is employed in which the gate capacitance of the first gate conductor layer 5 a to which the plate line wiring layer PL is connected is larger than the gate capacitance of the second gate conductor layer 5 b to which the word line wiring layer WL is connected, the memory cell area does not increase in plan view. Accordingly, a high-performance and highly integrated dynamic flash memory cell can be implemented.

(Feature 2)

Even when the diameter of the Si pillar 2 of the dynamic flash memory cell according to this embodiment is made smaller for miniaturization, a region in which the group of positive holes are present can be provided because an electric field is applied to the channel-layer P layer 53 not circumferentially to the entire surface but in one direction. Therefore, as the data retention property in “1” writing, an extended longer time can be attained. As a result, the duty ratio in a refresh operation can be significantly improved. When a group of a larger number of positive holes are stored in the channel-layer P layer 53, “1” write data is not lost even with a very small leak current, and a highly reliable memory device can be provided.

(Feature 3)

As described with reference to FIGS. 5BA to 5BC, when the plate line wiring layer is disposed so as to be shared among the Si pillars 2 adjacent to each other in the column direction, the design rule of the plate line wiring layer can be relaxed, and from the viewpoint of processes, the plate line wiring layer and the word line wiring layer in an upper layer above the plate line wiring layer can be easily processed.

(Feature 4)

In the dynamic flash memory cell according to this embodiment, the page erase operation described with reference to FIG. 4A to FIGS. 4DA-4DD are performed, in which rewriting is performed with an electric field much lower than in a flash memory. Accordingly, from the viewpoint of reliability, a limitation need not be put on the number of times rewriting is performed in the page erase operation.

Other Embodiments

Although the Si pillar is formed in the present invention, the Si pillar may be a semiconductor pillar made of a semiconductor material other than Si. This is similarly applicable to other embodiments according to the present invention.

In vertical NAND-type flash memory circuits, memory cells that are stacked in a plurality of stages in the vertical direction and each of which is constituted by a semiconductor pillar, which functions as the channel, and a tunnel oxide layer, a charge storage layer, an interlayer insulating layer, and a control conductor layer that surround the semiconductor pillar are formed. At the semiconductor pillars on both ends of these memory cells, a source line impurity layer corresponding to the source and a bit line impurity layer corresponding to the drain are disposed respectively. In addition, for one memory cell, when one of the memory cells on both sides of the one memory cell functions as the source, the other functions as the drain. Accordingly, the vertical NAND-type flash memory circuit is one type of SGT circuit. Therefore, the present invention is also applicable to a circuit in which a NAND-type flash memory circuit coexists.

To write “1”, electron-positive hole pairs may be generated by an impact ionization phenomenon using a gate-induced drain leakage (GIDL) current described in NPL 10 and NPL 11, and the floating body FB may be filled with the generated group of positive holes. This is similarly applicable to other embodiments according to the present invention.

Even with a structure in which the conductivity type that is the polarity of each of the N⁺ layers 3 a and 3 b and the P-layer Si pillar 2 in FIG. 1 is reversed, the operations of the dynamic flash memory can be performed. In this case, in the Si pillar 2 that is of N-type, the majority carriers are electrons. Therefore, a group of electrons generated by impact ionization are stored in the channel region 7, and a “1” state is set.

Various embodiments and modifications can be made to the present invention without departing from the spirit and scope of the present invention in a broad sense. The above-described embodiments are intended to explain examples of the present invention and are not intended to limit the scope of the present invention. Any of the above-described embodiments and modifications can be combined. Further, the above-described embodiments from which some of the constituent requirements are removed as needed are also within the scope of the technical spirit of the present invention.

INDUSTRIAL APPLICABILITY

With the memory device including a semiconductor element according to the present invention, a high-density and high-performance dynamic flash memory that is a memory device including an SGT can be obtained. 

1. A semiconductor element memory device that is a memory device comprising a plurality of memory cells arranged in a matrix, each of the memory cells comprising: a semiconductor base material that stands on a substrate in a vertical direction or that extends in a horizontal direction along the substrate; a first impurity layer and a second impurity layer that are disposed at respective ends of the semiconductor base material; a first gate insulating layer that is in contact with or in close vicinity to the first impurity layer and that partially or entirely surrounds an entire periphery of a side surface of the semiconductor base material between the first impurity layer and the second impurity layer; a second gate insulating layer that surrounds the entire periphery of the side surface of the semiconductor base material and that is in contact with or in close vicinity to the second impurity layer; a first gate conductor layer that partially covers the side surface of the semiconductor base material with the first gate insulating layer therebetween; a second gate conductor layer that covers the entire periphery of the side surface of the semiconductor base material with the second gate insulating layer therebetween; and a channel semiconductor layer that is the semiconductor base material and that is covered by the first gate insulating layer and the second gate insulating layer, wherein in each memory cell, voltages applied to the first gate conductor layer, the second gate conductor layer, the first impurity layer, and the second impurity layer are controlled to perform a write operation, an erase operation, and a read operation, the first impurity layer of the memory cell is connected to a source line wiring layer, the second impurity layer thereof is connected to a bit line wiring layer, the first gate conductor layer thereof is connected to a first driving control line wiring layer, and the second gate conductor layer thereof is connected to a word line wiring layer, and the first driving control line wiring layer and the word line wiring layer are disposed parallel to a row direction.
 2. The semiconductor element memory device according to claim 1, wherein the first driving control line wiring layer is shared among the semiconductor base materials adjacent to each other in a column direction.
 3. The semiconductor element memory device according to claim 1, wherein a first peripheral length, in plan view, of the semiconductor base material covered by the first gate insulating layer is shorter than a second peripheral length, in plan view, of the semiconductor base material covered by the second gate insulating layer.
 4. The semiconductor element memory device according to claim 1, wherein a first gate capacitance between the first gate conductor layer and the channel semiconductor layer is made larger than a second gate capacitance between the second gate conductor layer and the channel semiconductor layer.
 5. The semiconductor element memory device according to claim 1, wherein in the write operation, a group of positive holes generated by an impact ionization phenomenon or by a gate-induced drain leakage current are retained inside the channel semiconductor layer, and a voltage of the channel semiconductor layer is made equal to a first data retention voltage that is higher than the voltage of either the first impurity layer or the second impurity layer or that is higher than the voltages of both the first impurity layer and the second impurity layer, and in the erase operation, the voltages applied to the first impurity layer, the second impurity layer, the first gate conductor layer, and the second gate conductor layer are controlled to discharge the group of positive holes through either the first impurity layer or the second impurity layer or both the first impurity layer and the second impurity layer, and the voltage of the channel semiconductor layer is made equal to a second data retention voltage that is lower than the first data retention voltage. 